1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a silicon-on-insulator (SOI) semiconductor device and a fabrication method thereof that improves an electrostatic discharge (ESD) protection capability.
2. Description of the Conventional Art
Recently, a silicon-on-insulator (SOI) technique has been considered as one of the most effective techniques for improving performance of a very large scale integration (VLSI). According to the SOI technique, circuit elements of the integrated circuit are isolated by a buried oxide film, thereby latch up of transistors does not occur and junction capacitance decreases. Therefore, the SOI semiconductor device has an advantage that, due to the decrease of parasitic capacitance, the operation speed thereof is faster than an integrated circuit device of the same dimension provided on a bulk silicon substrate. Further, a semiconductor device using the SOI substrate is highly applicable to fabrication of a metal oxide semiconductor field effect transistor (MOSFET) under the size of 0.1 .mu.m due to its improvement of a short channel effect, intensive tolerance to radiation, a simple fabricating process and excellent device isolating property.
However, the problem in fabricating the integrated circuit using the SOI substrate is that the buried insulator which enables the integrated circuit device to have excellent property affects the ESD protection capability, which becomes hindrance to replace the bulk silicon substrate by the SOI substrate.
For reference, the comparison of the ESD protection capability of the bulk silicon substrate with that of the SOI substrate was disclosed in "Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers", p. 292-298 of Proceedings of 1994 IEEE/IRPS by Mansun Chan, Seling S. Yuen, Zhi-Jian Ma, Kelvin Y. Hu, Ping K. Ho, and Chenming Hu. As discussed therein the reason of deterioration of the ESD protection capability of the SOI substrate is that since an ESD protecting transistor provided in the SOI substrate includes a buried insulator (SiO.sub.2) formed under a drain thereof, p-n junction is not to be formed and thus there is no series resistance, while an ESD protecting transistor in the bulk silicon substrate has p-n junction between the substrate and a drain, thereby forming low series resistance. Further, when heat is generated during the ESD event, heat sink of a silicon oxide film which is the buried oxide film is inferior to the bulk silicon. Therefore, when fabricating the ESD protecting device by using the SOI substrate, as a silicon film on the buried oxidation becomes thick, the ESD protection capability improves. FIG. 1 illustrates the change of an ESD failure voltage in accordance with the thickness of the silicon film described in the above reference, wherein the numbers shown along an axis X indicate thickness of the silicon film formed on the buried insulator of the SOI substrate and the numbers along an axis Y show values of the ESD failure voltage. Here, as it goes to the right side of the axis X, the silicon film becomes thick. As shown therein, the thickness of the silicon film provided on the buried oxide film is proportional to the ESD failure voltage, which means that as the silicon film becomes thick, it becomes more tolerable to the ESD of a higher voltage. Accordingly, the more the ESD failure voltage increases, the higher reliability of the ESD protection capability becomes.